Electronic devices are being designed to use lower and lower power supply voltages in order to reduce the power drain for the devices and the heat generated therein. This is especially helpful in portable, battery operated devices such as cellular telephones, PDAs, MP3 Players, for example because they are both battery powered and highly compact, so that heat dissipation is a problem. In addition, the lower voltage supplies allow higher speed operation, because the voltage swing of the signal is smaller and will therefore take place in less time than when a higher supply voltage is used. Therefore, even circuits that are not intended for highly compact and battery powered mobile applications are using lower and lower voltage supplies in order to obtain the speed benefits as well as the reduced power supply requirements and lower heat dissipation, which allows for reduced ventilation requirements. In this continuum of redesigns at lower voltages, it is common to have some circuits for a particular system available at the lowest voltage whereas other components may not yet have been redesigned and require higher voltage supplies in order to operate. If these two devices are utilized in a common system, there needs to be a circuit interfacing the signal flow between them in order that the different power supply voltages, and therefore signal swings, can be accommodated. A signal level translator circuit meets this need. Typically, these circuits are bidirectional in nature so that the signal flow can occur from either device to the other device. Although devices having a pin for selection of the direction in which the signal flow is to occur are known, it is preferable to eliminate this pin, and therefore the cost associate therewith, and design the circuit to automatically detect the direction in which the signal flow will occur. Circuits that perform this function are known in the art.
A signal translation circuit for I2C logic, for example, which utilizes open drain circuits on either end of the signal translator generally use a directionless pass gate transistor signal translator. The principle for operation of this type of circuit is shown in FIG. 1 generally as 100. Terminal A is connected to a circuit operating at a first signal voltage and terminal B is connected to a circuit operating at a second, higher signal voltage. Each of the terminals is pulled up to its respective voltage VCCA or VCCB by a respective pull-up resistor 102, 114. The terminals are connected together via a pass transistor 110 which is a NMOS transistor having a gate bias 108. As will be seen in later described circuits, the gate bias voltage is commonly coupled to the chip enable signal. A one-shot circuit 106 has one input connected to the terminal A side of the pass transistor 110 and a second input connected to the B side of the pass transistor 110. If the signal on one terminal transitions from a high level to a low level, the other terminal is pulled down to that voltage via the pass transistor 110, which is biased in its ON state. However, due to the body effect, the pass transistor is not very effective in pulling up the other terminal to its respective voltage supply. The pull up resistors 102, 114 provides sufficient drive to maintain the voltage on terminal A or terminal B, respectively once the transition is made. The one-shot circuit detects the transition and operates one of the pull-up PMOS transistors 104,112 in order to pull the respective terminal up to its respective voltage supply. In view of the fact that one of the terminals will already be at its respective voltage supply level, both transistors 104,112 can be turned on at once, as it will have no effect on the terminal that is already at its respective voltage supply.
The gate of the pass transistor should be biased to a voltage which is approximately one volt above the lower of the two VCC supply voltages. If the bias voltage is too high, there will be undesirable feed-through current from the high voltage terminal to the low voltage terminal. If the voltage is too low, the ON resistance of the pass transistor will be too high. A known bias circuit is shown is FIG. 2 generally as 200. As discussed above, the bias supply is connected to the chip enable line and is active low. This chip enable signal is inverted through a pair of inverters INV1 and INV2 and applied to the gates of a PMOS transistor P1 and NMOS transistor N1 coupled between the voltage supply VCCB and ground. The drains of the two transistors are connected via resistor R1. Once PMOS P1 is turned on by way of ENABLE node being driven to a low state, it provides a pull-up current to the bias line BIAS for the pass transistor through resistor R1. The transition is also applied to PMOS transistor P8 and NMOS transistor N4 which have the gates coupled together and coupled to the enable input. The output on line s1 is coupled to the base of PNP transistor Q1 having its emitter coupled to the bias line and its collector coupled to ground. With enable low, the base of Q1 is biased to VCCA through P8 and Q1 clamps node BIAS to one VBE above VCCA. The inclusion of a bipolar transistor Q1 requires that this circuit be implemented in a BiCMOS process. In addition, power is dissipated through resistor R1 and the enable time is longer or else a higher current through resistor R1 is required.
A second known biasing circuit is shown in FIG. 3 generally as 300. In this circuit, a NMOS transistor N1 is coupled to the chip enabled signal via a pair of inverters INV1 and INV2. It switches a current source having a current I to the BIAS line. The transitions are provided by a PNP transistor having its emitter coupled to the BIAS line and collector coupled to ground and a base coupled to a reference voltage which is equal to the input voltage reference VCCA plus an offset voltage. In addition to requiring a BiCMOS process, it requires complex bias generators that have a long delay time or a higher current.
Previous implementation of the bias circuits such as the ones shown in FIGS. 2 and 3 have a high static current on the order of 200 uA and have relatively long enable times on the order of two microseconds for the pass gate to be biased on.
Accordingly, there is a need for a signal translator circuit that can be fabricated by an all CMOS process and which can have a faster enable time and a lower static current requirement.